Japanese Patent Application No. 50-84820 (Japanese Patent Laid-Open No. 52-8739) discloses a system which utilizes emitter coupled logic (ECL) and a diode (or a multi-emitter) matrix, and which selects or does not select the diode matrix in a two-dimensional or higher dimensional manner, in order to reduce the consumption of electric power and the number of elements in the decoder circuit.
The decoder circuit mentioned-above is advantageous with regard to reduced power consumption and to a reduced number of element compared to conventional decoder circuits. However, it has a defect in that the output level rises and falls slowly, since the decoder lines are very lengthy as they run over the groups of memory cells and, hence, possess a large capacitance. Therefore, when the reading level is higher than a point at which the output waveform rises slowly, the access time tends to be delayed.